Act as a Principal Embedded Hardware Architect, Robotics Eng...

Prompt

Act as a Principal Embedded Hardware Architect, Robotics Engineer, and Senior Web Graphics/UI Developer. Create a single, fully self-contained, and interactive HTML file (index.html) that showcases the complete hardware architecture and schematic visualizer for an Ultra-High-Performance Humanoid Robot Central Controller & Edge AI Supercomputer. The humanoid robot contains over 60 multi-axis actuators (BLDC/PMSM joints) and thousands of distributed sensors (tactile skin, stereo cameras, solid-state LiDAR, redundant 9-axis IMUs, and strain gauges). ### SYSTEM SPECIFICATIONS TO INCLUDE IN THE DESIGN: 1. High-Level AI & Perception Core: - Heterogeneous SoC: Dual AI Accelerators / NPUs (for on-device LLM/VLA foundation model inference). - High-speed memory: LPDDR5X / HBM subsystem. - High-throughput sensor interfaces: 8x MIPI CSI-2 / GMSL2 deserializers for stereoscopic vision & depth sensing. 2. Real-Time Motion Control & Sub-system Management: - High-performance UltraScale+ FPGA / Real-Time Dual-Core ARM Cortex-R8 for microsecond-level inverse kinematics & trajectory execution. - Deterministic communication buses: EtherCAT Master chip, 8x CAN-FD isolated transceivers, and Time-Sensitive Networking (TSN) Gigabit Ethernet. 3. Actuation & Joint Interface Subsystem: - Field Oriented Control (FOC) signal paths, dual-encoder feedback loops (magnetic + optical absolute encoders). - Emergency Stop (E-Stop) hardwired safety interlocking circuit. 4. Distributed Sensor Aggregation: - I3C / SPI multiplexer hub for tactile skin pressure arrays across limbs. 5. Power Delivery Network (PDN): - 48V to 12V / 5V / 3.3V / 1.8V / 0.85V (Vcore) high-efficiency synchronous buck converters with multi-stage EMI filtering, hot-swap protection, and redundant BMS telemetry. ### VISUAL & CODE REQUIREMENTS (Single HTML File): - Zero External Dependencies: Use pure HTML5, CSS3, and JavaScript with SVG and Canvas (No external frameworks that require internet or could fail). - Interactive Schematic & Architecture Map: * Render an interactive vector (SVG/Canvas) schematic showing all functional blocks, ICs, interconnects, high-speed differential pairs, and power rails. * Implement Pan and Zoom controls. * Component Interactivity: Clicking any block/IC (e.g., NPU, FPGA, EtherCAT PHY, Buck Converter, Isolated Gate Driver) must open an inspection drawer showing: - Chip Pinout & Signal Names - Voltage/Current tolerances and clock frequencies - Data flow direction and linked peripherals - Real-time Simulated Telemetry Dashboard: * Animated data packets moving along high-speed buses (EtherCAT packets, PCIe lanes). * An integrated Oscilloscope / Logic Analyzer canvas at the bottom showing simulated live PWM signals, CAN-FD frames, and bus voltages. * Real-time thermal and power draw monitor simulating load when AI inference is active. - Aesthetics: * Ultra-modern dark-mode aerospace/industrial engineering workstation UI (deep slate/charcoal background, neon cyan/amber/green accent lines, clean typography). Deliver the entire working project as ONE single, un-truncated block of HTML code containing all HTML, CSS, and JavaScript.