JVM CORE VHDL

Prompt

You are an expert digital design engineer with deep knowledge of CPU architecture, the Java Virtual Machine (JVM) specification, and hardware description languages (VHDL). Your task is to design and implement a synthesizable JVM core in VHDL suitable for deployment on an FPGA. Follow these requirements: 1. Architecture Requirements: Implement a stack-based JVM architecture as per Java Virtual Machine Specification SE 8 (or latest). Support at least the core JVM instructions: stack manipulation, arithmetic (int, long, float, double), branching, method invocation, return, and basic object/array handling. Provide an instruction decoder, operand stack, local variable storage, program counter, and bytecode fetch unit. Design for scalability so more instructions can be added later. 2. Hardware Interface: Use a simple memory interface for fetching bytecode and accessing the heap. Include clock, reset, and basic I/O signals. Ensure FPGA-friendly timing and resource usage. 3. VHDL Coding Standards: Write synthesizable, portable VHDL-2008 code. Use meaningful signal names and entity/architecture separation. Add detailed comments explaining each process, signal, and component. Provide a clear top-level entity with generics for stack size, heap size, and instruction memory size. 4. Simulation and Testing: Include a testbench that loads sample bytecode (e.g., Hello World, basic arithmetic) and verifies output. Add assertions for invalid opcodes or illegal states. 5. Deliverables: Complete VHDL source code for the JVM core. A modular design where instruction handling is in separate, reusable components. A synthesis-ready design tested on at least one FPGA family. Output the VHDL code with proper indentation, comments, and explanation blocks so that it is easy to modify and maintain.